/* -*- Mode: c -*- */
####################################################################################################
Core 0
####################################################################################################
Cumulative:        Cycles: 2100778               Instructions: 5000001               IPC: 2.38007

ICACHE_MISS                                         12        0.001%               12        0.001%
ICACHE_HIT                                     2171395       99.999%          2171395       99.999%
                                               2171407      100.000%          2171407      100.000%
                                                  1.00         1.00              1.00         1.00

ICACHE_MISS_ONPATH                                   7       58.333%                7       58.333%
ICACHE_MISS_OFFPATH                                  5       41.667%                5       41.667%
                                                    12      100.000%               12      100.000%
                                                  0.42         0.48              0.42         0.48

ICACHE_HIT_ONPATH                              1665580       76.706%          1665580       76.706%
ICACHE_HIT_OFFPATH                              505815       23.294%           505815       23.294%
                                               2171395      100.000%          2171395      100.000%
                                                  0.23         0.39              0.23         0.39

ICACHE_HIT_ONPATH_SAT_BY_OFFPATH                     0         -nan%                0         -nan%
ICACHE_HIT_ONPATH_SAT_BY_ONPATH                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

ICACHE_HIT_OFFPATH_SAT_BY_OFFPATH                    0         -nan%                0         -nan%
ICACHE_HIT_OFFPATH_SAT_BY_ONPATH                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DCACHE_MISS                                      51556        3.373%            51556        3.373%
DCACHE_ST_BUFFER_HIT                                 3        0.000%                3        0.000%
DCACHE_HIT                                     1476757       96.626%          1476757       96.626%
                                               1528316      100.000%          1528316      100.000%
                                                  1.93         1.90              1.93         1.90

DCACHE_MISS_ONPATH                               51556       84.703%            51556       84.703%
DCACHE_MISS_OFFPATH                               9311       15.297%             9311       15.297%
                                                 60867      100.000%            60867      100.000%
                                                  0.15         0.34              0.15         0.34

DCACHE_ST_BUFFER_HIT_ONPATH                          3      100.000%                3      100.000%
DCACHE_ST_BUFFER_HIT_OFFPATH                         0        0.000%                0        0.000%
                                                     3      100.000%                3      100.000%
                                                  0.00         0.00              0.00         0.00

DCACHE_HIT_ONPATH                              1476757       91.945%          1476757       91.945%
DCACHE_HIT_OFFPATH                              129376        8.055%           129376        8.055%
                                               1606133      100.000%          1606133      100.000%
                                                  0.08         0.26              0.08         0.26

DCACHE_HIT_ONPATH_SAT_BY_OFFPATH                     0         -nan%                0         -nan%
DCACHE_HIT_ONPATH_SAT_BY_ONPATH                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DCACHE_HIT_OFFPATH_SAT_BY_OFFPATH                    0         -nan%                0         -nan%
DCACHE_HIT_OFFPATH_SAT_BY_ONPATH                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DCACHE_MISS_LD                                   51517       99.924%            51517       99.924%
DCACHE_MISS_ST                                      39        0.076%               39        0.076%
                                                 51556      100.000%            51556      100.000%
                                                  0.00         0.03              0.00         0.03

DCACHE_MISS_LD_ONPATH                            51517       84.747%            51517       84.747%
DCACHE_MISS_LD_OFFPATH                            9272       15.253%             9272       15.253%
                                                 60789      100.000%            60789      100.000%
                                                  0.15         0.34              0.15         0.34

DCACHE_MISS_ST_ONPATH                               39       50.000%               39       50.000%
DCACHE_MISS_ST_OFFPATH                              39       50.000%               39       50.000%
                                                    78      100.000%               78      100.000%
                                                  0.50         0.50              0.50         0.50

DCACHE_MISS_WAITMEM                                  0                              0              

MEM_REQ_ROW_BUFFER_HITS                              0         -nan%                0         -nan%
MEM_REQ_ROW_BUFFER_MISSES                            0         -nan%                0         -nan%
MEM_REQ_ROW_BUFFER_CONFLICTS                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

SHADOW_ROW_BUFFER_HITS                               0                              0              

SHADOW_ROW_HIT_STALL_TIME                            0                              0              

CHANNEL0_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL1_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL2_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL3_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL4_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL5_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL6_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
CHANNEL7_BUS_BUSY_CYCLES                             0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CHANNEL_IDLE_DESPITE_READY_CMD                       0                              0              

MEM_NUM_TOTAL_BUS_CYCLES                             0                              0              

MEM_NUM_BANK_BUSY_PER_BUS_CYCLE                      0          -nan                0          -nan

CORE_NUM_BANK_BUSY_PER_BUS_CYCLE                     0          -nan                0          -nan

CHANNEL0_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL1_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL2_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL3_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL4_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL5_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL6_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
CHANNEL7_MEM_NUM_TOTAL_BUS_CYCLES                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CHANNEL0_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL1_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL2_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL3_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL4_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL5_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL6_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

CHANNEL7_MEM_NUM_BANK_BUSY_PER_BUS_CYCLE             0          -nan                0          -nan

BUS_DEMAND_ACCESS                                   49                             49              

BUS_PREF_ACCESS                                  17536                          17536              

BUS_ACCESS                                           0                              0              

L1_DEMAND_ACCESS                                 62740                          62740              

L1_PREF_ACCESS                                   35288                          35288              

L1_ACCESS                                        49123                          49123              

MLC_DEMAND_ACCESS                                    0                              0              

MLC_PREF_ACCESS                                      0                              0              

MLC_ACCESS                                           0                              0              

L1_HIT                                           17507       99.721%            17507       99.721%
L1_MISS                                             49        0.279%               49        0.279%
                                                 17556      100.000%            17556      100.000%
                                                  0.00         0.05              0.00         0.05

L1_HIT_ALL                                       31320       64.043%            31320       64.043%
L1_MISS_ALL                                      17585       35.957%            17585       35.957%
                                                 48905      100.000%            48905      100.000%
                                                  0.36         0.44              0.36         0.44

L1_DEMAND_MISS                                      49        0.279%               49        0.279%
L1_PREF_REQ_MISS                                 17536       99.721%            17536       99.721%
L1_WB_MISS                                           0        0.000%                0        0.000%
                                                 17585      100.000%            17585      100.000%
                                                  1.00         0.00              1.00         0.00

L1_DEMAND_HIT                                    17507       55.897%            17507       55.897%
L1_PREF_REQ_HIT                                      0        0.000%                0        0.000%
L1_WB_HIT                                        13813       44.103%            13813       44.103%
                                                 31320      100.000%            31320      100.000%
                                                  0.88         0.95              0.88         0.95

L1_MISS_ONPATH                                      33       67.347%               33       67.347%
L1_MISS_OFFPATH                                     16       32.653%               16       32.653%
                                                    49      100.000%               49      100.000%
                                                  0.33         0.43              0.33         0.43

L1_MISS_ALL_ONPATH                               17569       99.909%            17569       99.909%
L1_MISS_ALL_OFFPATH                                 16        0.091%               16        0.091%
                                                 17585      100.000%            17585      100.000%
                                                  0.00         0.03              0.00         0.03

L1_HIT_ONPATH                                    16006       91.426%            16006       91.426%
L1_HIT_OFFPATH                                    1501        8.574%             1501        8.574%
                                                 17507      100.000%            17507      100.000%
                                                  0.09         0.27              0.09         0.27

L1_HIT_ALL_ONPATH                                29819       95.208%            29819       95.208%
L1_HIT_ALL_OFFPATH                                1501        4.792%             1501        4.792%
                                                 31320      100.000%            31320      100.000%
                                                  0.05         0.21              0.05         0.21

L1_HIT_ONPATH_SAT_BY_OFFPATH                         0         -nan%                0         -nan%
L1_HIT_ONPATH_SAT_BY_ONPATH                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_HIT_OFFPATH_SAT_BY_OFFPATH                        0         -nan%                0         -nan%
L1_HIT_OFFPATH_SAT_BY_ONPATH                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_HIT_ONPATH_IFETCH_SAT_BY_OFFPATH                  0         -nan%                0         -nan%
L1_HIT_ONPATH_IFETCH_SAT_BY_ONPATH                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_HIT_ONPATH_DATA_SAT_BY_OFFPATH                    0         -nan%                0         -nan%
L1_HIT_ONPATH_DATA_SAT_BY_ONPATH                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_FILL_OFFPATH_IFETCH                               0                              0              

L1_FILL_OFFPATH_DATA                                 0                              0              

L1_FILL_OFFPATH                                      0                              0              

L1_USE_OFFPATH_IFETCH                                0          -nan                0          -nan

L1_USE_OFFPATH_DATA                                  0          -nan                0          -nan

L1_USE_OFFPATH                                       0          -nan                0          -nan

JUST_L1_USE_OFFPATH                                  0          -nan                0          -nan

L1_FILL_ONPATH_IFETCH                                0                              0              

L1_FILL_ONPATH_DATA                                  0                              0              

L1_FILL_ONPATH                                       0                              0              

L1_USE_ONPATH_IFETCH                                 0          -nan                0          -nan

L1_USE_ONPATH_DATA                                   0          -nan                0          -nan

L1_USE_ONPATH                                        0          -nan                0          -nan

L1_CYCLE                                       2100778                        2100778              

L1_LINES                                   18339473725     8729.8485      18339473725     8729.8485

MLC_HIT                                              0         -nan%                0         -nan%
MLC_MISS                                             0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_HIT_ALL                                          0         -nan%                0         -nan%
MLC_MISS_ALL                                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_DEMAND_MISS                                      0         -nan%                0         -nan%
MLC_PREF_REQ_MISS                                    0         -nan%                0         -nan%
MLC_WB_MISS                                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_DEMAND_HIT                                       0         -nan%                0         -nan%
MLC_PREF_REQ_HIT                                     0         -nan%                0         -nan%
MLC_WB_HIT                                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_MISS_ONPATH                                      0         -nan%                0         -nan%
MLC_MISS_OFFPATH                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_MISS_ALL_ONPATH                                  0         -nan%                0         -nan%
MLC_MISS_ALL_OFFPATH                                 0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_HIT_ONPATH                                       0         -nan%                0         -nan%
MLC_HIT_OFFPATH                                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_HIT_ALL_ONPATH                                   0         -nan%                0         -nan%
MLC_HIT_ALL_OFFPATH                                  0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DCACHE_FILL_OFFPATH                                  0                              0              

DCACHE_USE_OFFPATH                                   0          -nan                0          -nan

DCACHE_FILL_ONPATH                                   0                              0              

DCACHE_USE_ONPATH                                    0          -nan                0          -nan

ICACHE_FILL_OFFPATH                                  0                              0              

ICACHE_USE_OFFPATH                                   0          -nan                0          -nan

ICACHE_FILL_ONPATH                                   0                              0              

ICACHE_USE_ONPATH                                    0          -nan                0          -nan

REQBUF_CREATE_ONPATH                             48330                          48330              

REQBUF_ONPATH_MATCH_OFFPATH                          0        0.0000                0        0.0000

REQBUF_CREATE_ONPATH_DATA                        16032                          16032              

REQBUF_ONPATH_MATCH_OFFPATH_DATA                     0        0.0000                0        0.0000

REQBUF_CREATE_ONPATH_IFETCH                          7                              7              

REQBUF_ONPATH_MATCH_OFFPATH_IFETCH                   0        0.0000                0        0.0000

REQBUF_CREATE_OFFPATH                             1517                           1517              

ONPATH_KICKED_OUT_OFFPATH                            0                              0              

ONPATH_KICKED_OUT_PREFETCH                           0                              0              

DIST_ICACHE_FILL_OFFPATH_USED                        0         -nan%                0         -nan%
DIST_ICACHE_FILL_OFFPATH_NOTUSED                     0         -nan%                0         -nan%
DIST_ICACHE_FILL_ONPATH_PARTIAL                      0         -nan%                0         -nan%
DIST_ICACHE_FILL_ONPATH                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_DCACHE_FILL_OFFPATH_USED                        0         -nan%                0         -nan%
DIST_DCACHE_FILL_OFFPATH_NOTUSED                     0         -nan%                0         -nan%
DIST_DCACHE_FILL_ONPATH_PARTIAL                      0         -nan%                0         -nan%
DIST_DCACHE_FILL_ONPATH                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_L1_FILL_OFFPATH_USED                            0         -nan%                0         -nan%
DIST_L1_FILL_OFFPATH_NOTUSED                         0         -nan%                0         -nan%
DIST_L1_FILL_ONPATH_PARTIAL                          0         -nan%                0         -nan%
DIST_L1_FILL_ONPATH                                  0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_JUST_L1_FILL_OFFPATH_USED                       0         -nan%                0         -nan%
DIST_JUST_L1_FILL_OFFPATH_NOTUSED                    0         -nan%                0         -nan%
DIST_JUST_L1_FILL_ONPATH_PARTIAL                     0         -nan%                0         -nan%
DIST_JUST_L1_FILL_ONPATH                             0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_REQBUF_OFFPATH_USED                             0        0.000%                0        0.000%
DIST_REQBUF_OFFPATH_NOTUSED                          0        0.000%                0        0.000%
DIST_REQBUF_ONPATH                               33575      100.000%            33575      100.000%
                                                 33575      100.000%            33575      100.000%
                                                  2.00         2.00              2.00         2.00

DIST2_REQBUF_OFFPATH_USED_PARTIAL                    0        0.000%                0        0.000%
DIST2_REQBUF_OFFPATH_USED_FULL                       0        0.000%                0        0.000%
DIST2_REQBUF_OFFPATH_NOTUSED                         0        0.000%                0        0.000%
DIST2_REQBUF_ONPATH                              33575      100.000%            33575      100.000%
                                                 33575      100.000%            33575      100.000%
                                                  3.00         3.00              3.00         3.00

DIST_ICACHE_FILL                                     0                              0              

DIST_DCACHE_FILL                                     0                              0              

DIST_L1_FILL                                         0                              0              

DIST_USED_OFFPATH_ICACHE                             0         -nan%                0         -nan%
DIST_NOTUSED_OFFPATH_ICACHE                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_USED_OFFPATH_DCACHE                             0         -nan%                0         -nan%
DIST_NOTUSED_OFFPATH_DCACHE                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_USED_OFFPATH_L1                                 0         -nan%                0         -nan%
DIST_NOTUSED_OFFPATH_L1                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_USED_OFFPATH_JUST_L1                            0         -nan%                0         -nan%
DIST_NOTUSED_OFFPATH_JUST_L1                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_OFFPATH_ICACHE_FULL                             0         -nan%                0         -nan%
DIST_OFFPATH_ICACHE_PARTIAL                          0         -nan%                0         -nan%
DIST_OFFPATH_ICACHE_NOTUSED                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_OFFPATH_DCACHE_FULL                             0         -nan%                0         -nan%
DIST_OFFPATH_DCACHE_PARTIAL                          0         -nan%                0         -nan%
DIST_OFFPATH_DCACHE_NOTUSED                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_OFFPATH_L1_FULL                                 0         -nan%                0         -nan%
DIST_OFFPATH_L1_PARTIAL                              0         -nan%                0         -nan%
DIST_OFFPATH_L1_NOTUSED                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIST_OFFPATH_JUST_L1_FULL                            0         -nan%                0         -nan%
DIST_OFFPATH_JUST_L1_PARTIAL                         0         -nan%                0         -nan%
DIST_OFFPATH_JUST_L1_NOTUSED                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_MISS_ONPATH_IFETCH                               0         -nan%                0         -nan%
MLC_MISS_ONPATH_DFETCH                               0         -nan%                0         -nan%
MLC_MISS_ONPATH_DSTORE                               0         -nan%                0         -nan%
MLC_MISS_ONPATH_IPRF                                 0         -nan%                0         -nan%
MLC_MISS_ONPATH_DPRF                                 0         -nan%                0         -nan%
MLC_MISS_ONPATH_WB                                   0         -nan%                0         -nan%
MLC_MISS_ONPATH_WB_NODIRTY                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_MISS_OFFPATH_IFETCH                              0         -nan%                0         -nan%
MLC_MISS_OFFPATH_DFETCH                              0         -nan%                0         -nan%
MLC_MISS_OFFPATH_DSTORE                              0         -nan%                0         -nan%
MLC_MISS_OFFPATH_IPRF                                0         -nan%                0         -nan%
MLC_MISS_OFFPATH_DPRF                                0         -nan%                0         -nan%
MLC_MISS_OFFPATH_WB                                  0         -nan%                0         -nan%
MLC_MISS_OFFPATH_WB_NODIRTY                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_HIT_ONPATH_IFETCH                                0         -nan%                0         -nan%
MLC_HIT_ONPATH_DFETCH                                0         -nan%                0         -nan%
MLC_HIT_ONPATH_DSTORE                                0         -nan%                0         -nan%
MLC_HIT_ONPATH_IPRF                                  0         -nan%                0         -nan%
MLC_HIT_ONPATH_DPRF                                  0         -nan%                0         -nan%
MLC_HIT_ONPATH_WB                                    0         -nan%                0         -nan%
MLC_HIT_ONPATH_WB_NODIRTY                            0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_HIT_OFFPATH_IFETCH                               0         -nan%                0         -nan%
MLC_HIT_OFFPATH_DFETCH                               0         -nan%                0         -nan%
MLC_HIT_OFFPATH_DSTORE                               0         -nan%                0         -nan%
MLC_HIT_OFFPATH_IPRF                                 0         -nan%                0         -nan%
MLC_HIT_OFFPATH_DPRF                                 0         -nan%                0         -nan%
MLC_HIT_OFFPATH_WB                                   0         -nan%                0         -nan%
MLC_HIT_OFFPATH_WB_NODIRTY                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_MISS_ONPATH_IFETCH                                7        0.040%                7        0.040%
L1_MISS_ONPATH_DFETCH                               19        0.108%               19        0.108%
L1_MISS_ONPATH_DSTORE                                7        0.040%                7        0.040%
L1_MISS_ONPATH_IPRF                                  0        0.000%                0        0.000%
L1_MISS_ONPATH_DPRF                              17536       99.812%            17536       99.812%
L1_MISS_ONPATH_WB                                    0        0.000%                0        0.000%
L1_MISS_ONPATH_WB_NODIRTY                            0        0.000%                0        0.000%
                                                 17569      100.000%            17569      100.000%
                                                  3.99         0.11              3.99         0.11

L1_MISS_OFFPATH_IFETCH                               5       31.250%                5       31.250%
L1_MISS_OFFPATH_DFETCH                              11       68.750%               11       68.750%
L1_MISS_OFFPATH_DSTORE                               0        0.000%                0        0.000%
L1_MISS_OFFPATH_IPRF                                 0        0.000%                0        0.000%
L1_MISS_OFFPATH_DPRF                                 0        0.000%                0        0.000%
L1_MISS_OFFPATH_WB                                   0        0.000%                0        0.000%
L1_MISS_OFFPATH_WB_NODIRTY                           0        0.000%                0        0.000%
                                                    16      100.000%               16      100.000%
                                                  0.69         0.27              0.69         0.27

L1_HIT_ONPATH_IFETCH                                 0        0.000%                0        0.000%
L1_HIT_ONPATH_DFETCH                             16006       53.677%            16006       53.677%
L1_HIT_ONPATH_DSTORE                                 0        0.000%                0        0.000%
L1_HIT_ONPATH_IPRF                                   0        0.000%                0        0.000%
L1_HIT_ONPATH_DPRF                                   0        0.000%                0        0.000%
L1_HIT_ONPATH_WB                                 13813       46.323%            13813       46.323%
L1_HIT_ONPATH_WB_NODIRTY                             0        0.000%                0        0.000%
                                                 29819      100.000%            29819      100.000%
                                                  2.85         1.99              2.85         1.99

L1_HIT_OFFPATH_IFETCH                                0        0.000%                0        0.000%
L1_HIT_OFFPATH_DFETCH                             1501      100.000%             1501      100.000%
L1_HIT_OFFPATH_DSTORE                                0        0.000%                0        0.000%
L1_HIT_OFFPATH_IPRF                                  0        0.000%                0        0.000%
L1_HIT_OFFPATH_DPRF                                  0        0.000%                0        0.000%
L1_HIT_OFFPATH_WB                                    0        0.000%                0        0.000%
L1_HIT_OFFPATH_WB_NODIRTY                            0        0.000%                0        0.000%
                                                  1501      100.000%             1501      100.000%
                                                  1.00         0.00              1.00         0.00

DRAM_CYCLES                                          0                              0              

DRAM_UNBLOCK_CYCLES                                  0          -nan                0          -nan

DRAM_UNBLOCK_PERIODS                                 0                              0              

MEM_REQ_BUFFER_FULL                                  0                              0              

MEM_REQ_BUFFER_FULL_DENIED_DEMAND                    0                              0              

CORE_MEM_BLOCKED                                     0                              0              

MEM_REQ_BUFFER_FULL_DENIED_IFETCH                    0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_DFETCH                    0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_DSTORE                    0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_IPRF                      0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_DPRF                      0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_WB                        0         -nan%                0         -nan%
MEM_REQ_BUFFER_FULL_DENIED_WB_NODIRTY                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_QUEUE_FULL                                       0                              0              

MEM_REQ_BUFFER_MISS                              49847       53.501%            49847       53.501%
MEM_REQ_BUFFER_HIT                               43323       46.499%            43323       46.499%
                                                 93170      100.000%            93170      100.000%
                                                  0.46         0.48              0.46         0.48

MEM_REQ_IFETCH                                      12        0.024%               12        0.024%
MEM_REQ_DFETCH                                   17537       35.182%            17537       35.182%
MEM_REQ_DSTORE                                       7        0.014%                7        0.014%
MEM_REQ_IPRF                                         0        0.000%                0        0.000%
MEM_REQ_DPRF                                     17536       35.180%            17536       35.180%
MEM_REQ_WB                                       14755       29.601%            14755       29.601%
MEM_REQ_WB_NODIRTY                                   0        0.000%                0        0.000%
                                                 49847      100.000%            49847      100.000%
                                                  3.24         1.70              3.24         1.70

LD_NO_FORWARD                                   969487       72.263%           969487       72.263%
FORWARDED_LD                                    372121       27.737%           372121       27.737%
                                               1341608      100.000%          1341608      100.000%
                                                  0.28         0.41              0.28         0.41

WRONGPATH_L1Q_REMOVALS                               0         -nan%                0         -nan%
WRONGPATH_BUSQ_REMOVALS                              0         -nan%                0         -nan%
WRONGPATH_MEMQ_REMOVALS                              0         -nan%                0         -nan%
WRONGPATH_L1FILLQ_REMOVALS                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

WRONGPATH_L1Q_DEMOTIONS                              0         -nan%                0         -nan%
WRONGPATH_BUSQ_DEMOTIONS                             0         -nan%                0         -nan%
WRONGPATH_MEMQ_DEMOTIONS                             0         -nan%                0         -nan%
WRONGPATH_L1FILLQ_DEMOTIONS                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

PROMOTION_QMLC                                       0         -nan%                0         -nan%
PROMOTION_QL1                                        0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

PROMOTION_QBUSOUT                                    0                              0              

PROMOTION_QMEM                                       0                              0              

PROMOTION_QL1FILL                                    0                              0              

PROMOTION_QMLC_FILL                                  0                              0              

NOPROMOTION_QMEM                                     0                              0              

NOPROMOTION_QL1FILL                                  0         -nan%                0         -nan%
NOPROMOTION_QMLC_FILL                                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

ICACHE_FILL_CORRECT_REQ                              7       58.333%                7       58.333%
ICACHE_FILL_INCORRECT_REQ                            5       41.667%                5       41.667%
                                                    12      100.000%               12      100.000%
                                                  0.42         0.48              0.42         0.48

MEM_REQ_INIT                                     49847                          49847              

MEM_REQ_COMPLETE                                 48897        0.9809            48897        0.9809

MEM_REQ_KILLED                                     949        0.0190              949        0.0190

MEM_REQ_COMPLETE_MLC                                 0        0.0000                0        0.0000

MEM_REQ_COMPLETE_L1                              31320        0.6283            31320        0.6283

MEM_REQ_COMPLETE_MEM                             17577        0.3526            17577        0.3526

MEM_REQ_INIT_ONPATH                              48330        0.9696            48330        0.9696

MEM_REQ_INIT_OFFPATH                              1517        0.0304             1517        0.0304

MEM_REQ_COMPLETE_ONPATH                          47380        0.9690            47380        0.9690

MEM_REQ_COMPLETE_OFFPATH                          1517        0.0310             1517        0.0310

MEM_REQ_INIT_IFETCH                                 12        0.024%               12        0.024%
MEM_REQ_INIT_DFETCH                              17537       35.182%            17537       35.182%
MEM_REQ_INIT_DSTORE                                  7        0.014%                7        0.014%
MEM_REQ_INIT_IPRF                                    0        0.000%                0        0.000%
MEM_REQ_INIT_DPRF                                17536       35.180%            17536       35.180%
MEM_REQ_INIT_WB                                  14755       29.601%            14755       29.601%
MEM_REQ_INIT_WB_NODIRTY                              0        0.000%                0        0.000%
                                                 49847      100.000%            49847      100.000%
                                                  3.24         1.70              3.24         1.70

MEM_REQ_COMPLETE_IFETCH                             12        0.025%               12        0.025%
MEM_REQ_COMPLETE_DFETCH                          17537       35.865%            17537       35.865%
MEM_REQ_COMPLETE_DSTORE                              0        0.000%                0        0.000%
MEM_REQ_COMPLETE_IPRF                                0        0.000%                0        0.000%
MEM_REQ_COMPLETE_DPRF                            17535       35.861%            17535       35.861%
MEM_REQ_COMPLETE_WB                              13813       28.249%            13813       28.249%
MEM_REQ_COMPLETE_WB_NODIRTY                          0        0.000%                0        0.000%
                                                 48897      100.000%            48897      100.000%
                                                  3.21         1.70              3.21         1.70

MEM_REQ_KILLED_IFETCH                                0        0.000%                0        0.000%
MEM_REQ_KILLED_DFETCH                                0        0.000%                0        0.000%
MEM_REQ_KILLED_DSTORE                                7        0.738%                7        0.738%
MEM_REQ_KILLED_IPRF                                  0        0.000%                0        0.000%
MEM_REQ_KILLED_DPRF                                  0        0.000%                0        0.000%
MEM_REQ_KILLED_WB                                  942       99.262%              942       99.262%
MEM_REQ_KILLED_WB_NODIRTY                            0        0.000%                0        0.000%
                                                   949      100.000%              949      100.000%
                                                  4.98         0.26              4.98         0.26

MEM_REQ_INIT_OFFPATH_IFETCH                          5        0.330%                5        0.330%
MEM_REQ_INIT_OFFPATH_DFETCH                       1512       99.670%             1512       99.670%
MEM_REQ_INIT_OFFPATH_DSTORE                          0        0.000%                0        0.000%
MEM_REQ_INIT_OFFPATH_IPRF                            0        0.000%                0        0.000%
MEM_REQ_INIT_OFFPATH_DPRF                            0        0.000%                0        0.000%
MEM_REQ_INIT_OFFPATH_WB                              0        0.000%                0        0.000%
MEM_REQ_INIT_OFFPATH_WB_NODIRTY                      0        0.000%                0        0.000%
                                                  1517      100.000%             1517      100.000%
                                                  1.00         0.00              1.00         0.00

MEM_REQ_INIT_ONPATH_IFETCH                           7        0.014%                7        0.014%
MEM_REQ_INIT_ONPATH_DFETCH                       16025       33.157%            16025       33.157%
MEM_REQ_INIT_ONPATH_DSTORE                           7        0.014%                7        0.014%
MEM_REQ_INIT_ONPATH_IPRF                             0        0.000%                0        0.000%
MEM_REQ_INIT_ONPATH_DPRF                         17536       36.284%            17536       36.284%
MEM_REQ_INIT_ONPATH_WB                           14755       30.530%            14755       30.530%
MEM_REQ_INIT_ONPATH_WB_NODIRTY                       0        0.000%                0        0.000%
                                                 48330      100.000%            48330      100.000%
                                                  3.31         1.68              3.31         1.68

MEM_REQ_MATCH_IFETCH                                 0        0.000%                0        0.000%
MEM_REQ_MATCH_DFETCH                             43317       99.986%            43317       99.986%
MEM_REQ_MATCH_DSTORE                                 6        0.014%                6        0.014%
MEM_REQ_MATCH_IPRF                                   0        0.000%                0        0.000%
MEM_REQ_MATCH_DPRF                                   0        0.000%                0        0.000%
MEM_REQ_MATCH_WB                                     0        0.000%                0        0.000%
MEM_REQ_MATCH_WB_NODIRTY                             0        0.000%                0        0.000%
                                                 43323      100.000%            43323      100.000%
                                                  1.00         0.01              1.00         0.01

MEM_REQ_COMPLETE_OFFPATH_IFETCH                      5        0.330%                5        0.330%
MEM_REQ_COMPLETE_OFFPATH_DFETCH                   1512       99.670%             1512       99.670%
MEM_REQ_COMPLETE_OFFPATH_DSTORE                      0        0.000%                0        0.000%
MEM_REQ_COMPLETE_OFFPATH_IPRF                        0        0.000%                0        0.000%
MEM_REQ_COMPLETE_OFFPATH_DPRF                        0        0.000%                0        0.000%
MEM_REQ_COMPLETE_OFFPATH_WB                          0        0.000%                0        0.000%
MEM_REQ_COMPLETE_OFFPATH_WB_NODIRTY                  0        0.000%                0        0.000%
                                                  1517      100.000%             1517      100.000%
                                                  1.00         0.00              1.00         0.00

MEM_REQ_COMPLETE_ONPATH_IFETCH                       7        0.015%                7        0.015%
MEM_REQ_COMPLETE_ONPATH_DFETCH                   16025       33.822%            16025       33.822%
MEM_REQ_COMPLETE_ONPATH_DSTORE                       0        0.000%                0        0.000%
MEM_REQ_COMPLETE_ONPATH_IPRF                         0        0.000%                0        0.000%
MEM_REQ_COMPLETE_ONPATH_DPRF                     17535       37.009%            17535       37.009%
MEM_REQ_COMPLETE_ONPATH_WB                       13813       29.154%            13813       29.154%
MEM_REQ_COMPLETE_ONPATH_WB_NODIRTY                   0        0.000%                0        0.000%
                                                 47380      100.000%            47380      100.000%
                                                  3.28         1.68              3.28         1.68

MEM_REQ_COMPLETE_MEM_IFETCH                         12        0.068%               12        0.068%
MEM_REQ_COMPLETE_MEM_DFETCH                         30        0.171%               30        0.171%
MEM_REQ_COMPLETE_MEM_DSTORE                          0        0.000%                0        0.000%
MEM_REQ_COMPLETE_MEM_IPRF                            0        0.000%                0        0.000%
MEM_REQ_COMPLETE_MEM_DPRF                        17535       99.761%            17535       99.761%
MEM_REQ_COMPLETE_MEM_WB                              0        0.000%                0        0.000%
MEM_REQ_COMPLETE_MEM_WB_NODIRTY                      0        0.000%                0        0.000%
                                                 17577      100.000%            17577      100.000%
                                                  3.99         0.12              3.99         0.12

MEM_REQ_COMPLETE_MEM_BW_PREFETCHABLE                 0                              0              

MEM_REQ_COMPLETE_MEM_MATCHED_BW_PREF                 0                              0              

MEM_REQ_COMPLETE_L1_IFETCH                           0        0.000%                0        0.000%
MEM_REQ_COMPLETE_L1_DFETCH                       17507       55.897%            17507       55.897%
MEM_REQ_COMPLETE_L1_DSTORE                           0        0.000%                0        0.000%
MEM_REQ_COMPLETE_L1_IPRF                             0        0.000%                0        0.000%
MEM_REQ_COMPLETE_L1_DPRF                             0        0.000%                0        0.000%
MEM_REQ_COMPLETE_L1_WB                           13813       44.103%            13813       44.103%
MEM_REQ_COMPLETE_L1_WB_NODIRTY                       0        0.000%                0        0.000%
                                                 31320      100.000%            31320      100.000%
                                                  2.76         1.99              2.76         1.99

MEM_REQ_COMPLETE_MLC_IFETCH                          0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_DFETCH                          0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_DSTORE                          0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_IPRF                            0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_DPRF                            0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_WB                              0         -nan%                0         -nan%
MEM_REQ_COMPLETE_MLC_WB_NODIRTY                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLP_CLUSTERS                                    0                              0              

CORE_MLP                                       1608762                        1608762              

CORE_MLP_IFETCH                                      0                              0              

CORE_MLP_DFETCH                                      0                              0              

CORE_MLP_DSTORE                                      0                              0              

CORE_MLP_IPRF                                        0                              0              

CORE_MLP_DPRF                                        0                              0              

CORE_MLP_WB                                          0                              0              

CORE_MLP_WB_NODIRTY                                  0                              0              

CORE_MLP_0                                     1082741       51.540%          1082741       51.540%
CORE_MLP_1                                      856257       40.759%           856257       40.759%
CORE_MLP_2                                       58302        2.775%            58302        2.775%
CORE_MLP_3                                       18365        0.874%            18365        0.874%
CORE_MLP_4                                       15949        0.759%            15949        0.759%
CORE_MLP_5                                       13513        0.643%            13513        0.643%
CORE_MLP_6                                       11291        0.537%            11291        0.537%
CORE_MLP_7                                       11458        0.545%            11458        0.545%
CORE_MLP_8                                       11011        0.524%            11011        0.524%
CORE_MLP_9                                       10291        0.490%            10291        0.490%
CORE_MLP_10                                       7556        0.360%             7556        0.360%
CORE_MLP_11                                       3369        0.160%             3369        0.160%
CORE_MLP_12                                        608        0.029%              608        0.029%
CORE_MLP_13                                         67        0.003%               67        0.003%
CORE_MLP_14                                          0        0.000%                0        0.000%
CORE_MLP_15                                          0        0.000%                0        0.000%
CORE_MLP_16                                          0        0.000%                0        0.000%
CORE_MLP_17                                          0        0.000%                0        0.000%
CORE_MLP_18                                          0        0.000%                0        0.000%
CORE_MLP_19                                          0        0.000%                0        0.000%
CORE_MLP_20                                          0        0.000%                0        0.000%
CORE_MLP_21                                          0        0.000%                0        0.000%
CORE_MLP_22                                          0        0.000%                0        0.000%
CORE_MLP_23                                          0        0.000%                0        0.000%
CORE_MLP_24                                          0        0.000%                0        0.000%
CORE_MLP_25                                          0        0.000%                0        0.000%
CORE_MLP_26                                          0        0.000%                0        0.000%
CORE_MLP_27                                          0        0.000%                0        0.000%
CORE_MLP_28                                          0        0.000%                0        0.000%
CORE_MLP_29                                          0        0.000%                0        0.000%
CORE_MLP_30                                          0        0.000%                0        0.000%
CORE_MLP_31                                          0        0.000%                0        0.000%
CORE_MLP_32                                          0        0.000%                0        0.000%
                                               2100778      100.000%          2100778      100.000%
                                                  0.77         1.34              0.77         1.34

MEM_QUEUE_OCC_0                                      0         -nan%                0         -nan%
MEM_QUEUE_OCC_4                                      0         -nan%                0         -nan%
MEM_QUEUE_OCC_8                                      0         -nan%                0         -nan%
MEM_QUEUE_OCC_12                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_16                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_20                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_24                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_28                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_32                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_36                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_40                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_44                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_48                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_52                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_56                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_60                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_64                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_68                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_72                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_76                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_80                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_84                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_88                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_92                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_96                                     0         -nan%                0         -nan%
MEM_QUEUE_OCC_100                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_104                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_108                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_112                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_116                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_120                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_124                                    0         -nan%                0         -nan%
MEM_QUEUE_OCC_128                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

OPEN_PAGE_HIT                                        0         -nan%                0         -nan%
CLOSED_PAGE_MISS                                     0         -nan%                0         -nan%
WRONG_PAGE_MISS                                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L0_LD_BANK_BLOCK                                     0         -nan%                0         -nan%
L0_LD_BANK_AVAIL                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L0_ST_BANK_BLOCK                                     0         -nan%                0         -nan%
L0_ST_BANK_AVAIL                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L0_LD_CACHE_BLOCK                                    0         -nan%                0         -nan%
L0_LD_CACHE_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_LD_BANK_BLOCK                                    0         -nan%                0         -nan%
MLC_LD_BANK_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_ST_BANK_BLOCK                                    0         -nan%                0         -nan%
MLC_ST_BANK_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_LD_CACHE_BLOCK                                   0         -nan%                0         -nan%
MLC_LD_CACHE_AVAIL                                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_ST_CACHE_BLOCK                                   0         -nan%                0         -nan%
MLC_ST_CACHE_AVAIL                                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_LD_BANK_BLOCK                                   218        0.617%              218        0.617%
L1_LD_BANK_AVAIL                                 35092       99.383%            35092       99.383%
                                                 35310      100.000%            35310      100.000%
                                                  0.99         0.99              0.99         0.99

L1_ST_BANK_BLOCK                                     0        0.000%                0        0.000%
L1_ST_BANK_AVAIL                                 13813      100.000%            13813      100.000%
                                                 13813      100.000%            13813      100.000%
                                                  1.00         1.00              1.00         1.00

L1_LD_CACHE_BLOCK                                    0         -nan%                0         -nan%
L1_LD_CACHE_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_ST_CACHE_BLOCK                                    0         -nan%                0         -nan%
L1_ST_CACHE_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_LD_BANK_BLOCK                                    0         -nan%                0         -nan%
MEM_LD_BANK_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_ST_BANK_BLOCK                                    0         -nan%                0         -nan%
MEM_ST_BANK_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_PF_BANK_BLOCK                                    0         -nan%                0         -nan%
MEM_PF_BANK_AVAIL                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L0_FILL                                              0                              0              

L1_FILL                                          17577      100.000%            17577      100.000%
L1_WB_FILL                                           0        0.000%                0        0.000%
                                                 17577      100.000%            17577      100.000%
                                                  0.00         0.00              0.00         0.00

L1_DEMAND_FILL                                      42        0.239%               42        0.239%
L1_PREF_FILL                                     17535       99.761%            17535       99.761%
                                                 17577      100.000%            17577      100.000%
                                                  1.00         1.00              1.00         1.00

MLC_FILL                                             0         -nan%                0         -nan%
MLC_WB_FILL                                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MLC_DEMAND_FILL                                      0         -nan%                0         -nan%
MLC_PREF_FILL                                        0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

NORESET_L1_FILL                                  17577                          17577              

NORESET_L1_FILL_NONPREF                             42                             42              

NORESET_L1_FILL_PREF                             17535                          17535              

NORESET_L1_EVICT                                  1193                           1193              

NORESET_L1_EVICT_NONPREF                            40                             40              

NORESET_L1_EVICT_PREF_USED                        1153                           1153              

NORESET_L1_EVICT_PREF_UNUSED                         0                              0              

NORESET_L1_PREF_USED                             17504                          17504              

ORACLE_OFFPATH_DC_FILL                               0                              0              

ORACLE_OFFPATH_IC_FILL                               0                              0              

ORACLE_OFFPATH_L1_FILL                               0                              0              

UPDATE_EVENT_QUEUE_PROCESS                           0                              0              

INSERT_EVENT_QUEUE_PROCESS                           0                              0              

ICFILL_AFTER_REDIRECT                                0                              0              

EVENT_QUEUE_MATCH_ADD_REQ                            0                              0              

DC_PREF_CACHE_INSERT_REQ                             0                              0              

DC_PREF_REQ_DCACHE_HIT                               0         -nan%                0         -nan%
DC_PREF_REQ_PREF_CACHE_HIT                           0         -nan%                0         -nan%
DC_PREF_REQ_L1_MISS                                  0         -nan%                0         -nan%
DC_PREF_REQ_CORR                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DC_PREF_CACHE_INSERT                                 0                              0              

DC_PREF_CACHE_HIT_PER                                0        0.000%                0        0.000%

DC_PREF_CACHE_HIT_PER_OFFPATH                        0        0.000%                0        0.000%

DC_PREF_CACHE_HIT                                    0                              0              

DC_PREF_CACHE_HIT_OFFPATH                            0                              0              

DC_PREF_HIT_L1_MISS                                  0                              0              

IC_PREF_CACHE_HIT_PER                                0        0.000%                0        0.000%

IC_PREF_CACHE_HIT_PER_OFFPATH                        0        0.000%                0        0.000%

IC_PREF_CACHE_HIT                                    0                              0              

IC_PREF_CACHE_HIT_OFFPATH                            0                              0              

L1_PREF_CACHE_HIT_PER                                0        0.000%                0        0.000%

L1_PREF_CACHE_HIT_PER_OFFPATH                        0        0.000%                0        0.000%

L1_PREF_CACHE_HIT                                    0                              0              

L1_PREF_CACHE_HIT_OFFPATH                            0                              0              

DC_PREF_CACHE_FILL                                   0                              0              

DC_PREF_MOVE_DC                                      0         -nan%                0         -nan%

DC_PREF_MOVE_L1                                      0         -nan%                0         -nan%

IC_PREF_CACHE_FILL                                   0                              0              

IC_PREF_MOVE_IC                                      0         -nan%                0         -nan%

IC_PREF_MOVE_L1                                      0         -nan%                0         -nan%

L1_PREF_CACHE_FILL                                   0                              0              

L1_PREF_MOVE_L1                                      0         -nan%                0         -nan%

OFF_PATH_CONFIRMED                               26792                          26792              

OFF_PATH_NO_FILL_L1                                  0                              0              

WB_L1_MISS_FILL_L1                                   0                              0              

WB_MLC_MISS_FILL_MLC                                 0                              0              

ICACHE_EVICT_REQ_WB_L1                               0                              0              

DCACHE_EVICT_REQ_WB_L1                               0                              0              

DCACHE_EVICT_REQ_WB_L1_NOREAD                        0                              0              

L1_FILL_SKIPPED                                      0                              0              

MLC_FILL_SKIPPED                                     0                              0              

DCACHE_FILL                                      17537                          17537              

DCACHE_WB_REQ                                    13813        0.7876            13813        0.7876

DCACHE_WB_REQ_DIRTY                              13813      100.000%            13813      100.000%
DCACHE_WB_REQ_NODIRTY                                0        0.000%                0        0.000%
                                                 13813      100.000%            13813      100.000%
                                                  0.00         0.00              0.00         0.00

ICACHE_FILL                                          7                              7              

ICACHE_WB_REQ                                        0        0.0000                0        0.0000

L1_FILL_DIRTY                                      942        0.0536              942        0.0536

MLC_FILL_DIRTY                                       0          -nan                0          -nan

MEM_REQ_DENIED_NULL                                  0         -nan%                0         -nan%
MEM_REQ_DENIED_INST_OUTOF_CS                         0         -nan%                0         -nan%
MEM_REQ_DENIED_DATA_IN_CS                            0         -nan%                0         -nan%
MEM_REQ_DENIED_DATA_OUTOF_RANGE                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_REQ_DENIED                                       0         -nan%                0         -nan%
MEM_REQ_NOT_DENIED                                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DEMAND_HIT_WB_STALL                                  0                              0              

EXCLUSION_VIOLATED_OSR                               0         -nan%                0         -nan%
EXCLUSION_VIOLATED_NOTOSR                            0         -nan%                0         -nan%
EXCLUSION_NOT_VIOLATED                               0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DIRTY_WRITE_TO_ICACHE                                0                              0              

STREAM_DC_HIT_NOSEND                                 0         -nan%                0         -nan%
STREAM_WBQDC_HIT_NOSEND                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

STREAM_DCACHE_PREF_HIT                               0                              0              

PREF_DC_HIT_ON_INSERT                                0         -nan%                0         -nan%
PREF_L1_HIT_ON_INSERT                                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_NEWREQ_MATCHED_MLC_REQ                            0                              0              

MLC_NEWREQ_MATCHED_L2_PREF                           0                              0              

MLC_NEWREQ_MATCHED_L2_PREF_MLC_HIT                   0          -nan                0          -nan

NEWREQ_WB_MATCH_IGNORED                              0                              0              

DEMAND_MATCH_WB_NEW_DONE_FUNC                        0         -nan%                0         -nan%
DEMAND_MATCH_WB_NEW_DONE_FUNC_NULL                   0         -nan%                0         -nan%
DEMAND_MATCH_WB_DONE_FUNC_NOT_SAME                   0         -nan%                0         -nan%
DEMAND_MATCH_WB_DONE_FUNC_SAME                       0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DEMAND_MATCH_WB                                      0         -nan%                0         -nan%
DEMAND_MATCH_WB_NODIRTY                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DEMAND_MATCH_WBALL_IFETCH                            0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_DFETCH                            0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_DSTORE                            0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_IPRF                              0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_DPRF                              0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_WB                                0         -nan%                0         -nan%
DEMAND_MATCH_WBALL_WB_NODIRTY                        0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DEMAND_MATCH_WB_IFETCH                               0         -nan%                0         -nan%
DEMAND_MATCH_WB_DFETCH                               0         -nan%                0         -nan%
DEMAND_MATCH_WB_DSTORE                               0         -nan%                0         -nan%
DEMAND_MATCH_WB_IPRF                                 0         -nan%                0         -nan%
DEMAND_MATCH_WB_DPRF                                 0         -nan%                0         -nan%
DEMAND_MATCH_WB_WB                                   0         -nan%                0         -nan%
DEMAND_MATCH_WB_WB_NODIRTY                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DEMAND_MATCH_WB_ND_IFETCH                            0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_DFETCH                            0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_DSTORE                            0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_IPRF                              0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_DPRF                              0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_WB                                0         -nan%                0         -nan%
DEMAND_MATCH_WB_ND_WB_NODIRTY                        0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

WB_MATCH_DEMAND                                      0        0.000%                0        0.000%
WB_MATCH_PREF                                        0        0.000%                0        0.000%
WB_MATCH_WB                                          0        0.000%                0        0.000%
WB_MATCH_WB_FILTERED                             43258      100.000%            43258      100.000%
                                                 43258      100.000%            43258      100.000%
                                                  3.00         3.00              3.00         3.00

WB_COMING_BACK_FROM_MEM                              0                              0              

WB_COMING_BACK_FROM_L1                               0                              0              

WB_COMING_BACK_FROM_MLC                              0                              0              

MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH                0        0.000%                0        0.000%
MEM_REQ_MATCH_OFF_PATH_HIT_BY_ON_PATH_ETC         43323      100.000%            43323      100.000%
                                                 43323      100.000%            43323      100.000%
                                                  1.00         1.00              1.00         1.00

TOTAL_ONPATH_ICACHE_FILLS                            0                              0              

TOTAL_ONPATH_DCACHE_FILLS                            0                              0              

TOTAL_ONPATH_L1_FILLS                                0                              0              

PER1K_ONPATH_ICACHE_FILLS                            0        0.0000                0        0.0000

PER1K_ONPATH_DCACHE_FILLS                            0        0.0000                0        0.0000

PER1K_ONPATH_L1_FILLS                                0        0.0000                0        0.0000

PER1K_L1_DEMAND_MISS_ONPATH                         33        0.0066               33        0.0066

PER1K_L1_DEMAND_MISS_OFFPATH                        16        0.0032               16        0.0032

L2_IDEAL_FILL_L1                                     0         -nan%                0         -nan%
L2_IDEAL_MISS_L2                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L2_IDEAL_FILL_ICACHE                                 0         -nan%                0         -nan%
L2_IDEAL_MISS_ICACHE                                 0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

HPS_MISS_DELTA__0                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__1                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__2                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__3                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__4                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__5                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__6                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__7                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__8                                    0         -nan%                0         -nan%
HPS_MISS_DELTA__9                                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

HPS_HIT_DELTA__0                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__1                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__2                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__3                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__4                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__5                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__6                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__7                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__8                                     0         -nan%                0         -nan%
HPS_HIT_DELTA__9                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DC_MISS_DELTA__0                                     0         -nan%                0         -nan%
DC_MISS_DELTA__1                                     0         -nan%                0         -nan%
DC_MISS_DELTA__2                                     0         -nan%                0         -nan%
DC_MISS_DELTA__3                                     0         -nan%                0         -nan%
DC_MISS_DELTA__4                                     0         -nan%                0         -nan%
DC_MISS_DELTA__5                                     0         -nan%                0         -nan%
DC_MISS_DELTA__6                                     0         -nan%                0         -nan%
DC_MISS_DELTA__7                                     0         -nan%                0         -nan%
DC_MISS_DELTA__8                                     0         -nan%                0         -nan%
DC_MISS_DELTA__9                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

ONE_MORE_SUCESS                                      0         -nan%                0         -nan%
ONE_MORE_DISCARDED_L0CACHE                           0         -nan%                0         -nan%
ONE_MORE_DISCARDED_MEM_REQ_FULL                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

PREF_L1_TOTAL_SENT                               17536                          17536              

PREF_L1_TOTAL_USED                               17504       99.823%            17504       99.823%
PREF_L1_TOTAL_PARTIAL_USED                           0        0.000%                0        0.000%
PREF_L1_TOTAL_NOT_USED                              31        0.177%               31        0.177%
PREF_L1_TOTAL_DROPPED                                0        0.000%                0        0.000%
                                                 17535      100.000%            17535      100.000%
                                                  0.00         0.08              0.00         0.08

PREF_MLC_TOTAL_SENT                                  0                              0              

PREF_MLC_TOTAL_USED                                  0         -nan%                0         -nan%
PREF_MLC_TOTAL_PARTIAL_USED                          0         -nan%                0         -nan%
PREF_MLC_TOTAL_NOT_USED                              0         -nan%                0         -nan%
PREF_MLC_TOTAL_DROPPED                               0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_PREF_REQ_MISS                               0         -nan%                0         -nan%
CORE_MLC_DEMAND_MISS                                 0         -nan%                0         -nan%
CORE_MLC_WB_MISS                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_PREF_REQ_HIT                                0         -nan%                0         -nan%
CORE_MLC_DEMAND_HIT                                  0         -nan%                0         -nan%
CORE_MLC_WB_HIT                                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_HIT                                         0         -nan%                0         -nan%
CORE_MLC_MISS                                        0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_FILL                                        0         -nan%                0         -nan%
CORE_MLC_WB_FILL                                     0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_DEMAND_FILL                                 0         -nan%                0         -nan%
CORE_MLC_PREF_FILL                                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MLC_PREF_FILL_USED                              0         -nan%                0         -nan%
CORE_MLC_PREF_FILL_PARTIAL_USED                      0         -nan%                0         -nan%
CORE_MLC_PREF_FILL_NOT_USED                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_L1_PREF_REQ_MISS                            17536       99.721%            17536       99.721%
CORE_L1_DEMAND_MISS                                 49        0.279%               49        0.279%
CORE_L1_WB_MISS                                      0        0.000%                0        0.000%
                                                 17585      100.000%            17585      100.000%
                                                  0.00         0.05              0.00         0.05

CORE_L1_PREF_REQ_HIT                                 0        0.000%                0        0.000%
CORE_L1_DEMAND_HIT                               17507       55.897%            17507       55.897%
CORE_L1_WB_HIT                                   13813       44.103%            13813       44.103%
                                                 31320      100.000%            31320      100.000%
                                                  1.44         1.08              1.44         1.08

CORE_L1_HIT                                      17507       99.721%            17507       99.721%
CORE_L1_MISS                                        49        0.279%               49        0.279%
                                                 17556      100.000%            17556      100.000%
                                                  0.00         0.05              0.00         0.05

CORE_L1_FILL                                     17577      100.000%            17577      100.000%
CORE_L1_WB_FILL                                      0        0.000%                0        0.000%
                                                 17577      100.000%            17577      100.000%
                                                  0.00         0.00              0.00         0.00

CORE_L1_DEMAND_FILL                                 42        0.239%               42        0.239%
CORE_L1_PREF_FILL                                17535       99.761%            17535       99.761%
                                                 17577      100.000%            17577      100.000%
                                                  1.00         1.00              1.00         1.00

CORE_L1_PREF_FILL_USED                           17504       99.823%            17504       99.823%
CORE_L1_PREF_FILL_PARTIAL_USED                       0        0.000%                0        0.000%
CORE_L1_PREF_FILL_NOT_USED                          31        0.177%               31        0.177%
                                                 17535      100.000%            17535      100.000%
                                                  0.00         0.08              0.00         0.08

CORE_L1_DEMAND_USED_POS0                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS1                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS2                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS3                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS4                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS5                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS6                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS7                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS8                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS9                             0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS10                            0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS11                            0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS12                            0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS13                            0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS14                            0         -nan%                0         -nan%
CORE_L1_DEMAND_USED_POS15                            0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_L1_PREF_USED_POS0                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS1                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS2                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS3                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS4                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS5                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS6                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS7                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS8                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS9                               0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS10                              0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS11                              0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS12                              0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS13                              0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS14                              0         -nan%                0         -nan%
CORE_L1_PREF_USED_POS15                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_TOTAL_SETS_ALL_INTERVALS                        0                              0              

CORE_L1_AVG_NUM_WAYS                                 0          -nan                0          -nan

L1_PARTITION_INTERVALS                               0                              0              

NORESET_L1_PARTITION                                 0                              0              

L1_SHADOW_ACCESS                                     0                              0              

L1_SHADOW_ACCESS_STALLING                            0                              0              

L1_SHADOW_ACCESS_DEMAND                              0                              0              

L1_SHADOW_HIT                                        0                              0              

L1_SHADOW_HIT_STALLING                               0                              0              

L1_SHADOW_HIT_DEMAND                                 0                              0              

L1_SHADOW_UNTIMELY_HIT                               0                              0              

L1_SHADOW_UNTIMELY_HIT_STALLING                      0                              0              

L1_SHADOW_UNTIMELY_HIT_DEMAND                        0                              0              

L1_SHADOW_HIT_POS0                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS1                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS2                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS3                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS4                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS5                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS6                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS7                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS8                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS9                                   0         -nan%                0         -nan%
L1_SHADOW_HIT_POS10                                  0         -nan%                0         -nan%
L1_SHADOW_HIT_POS11                                  0         -nan%                0         -nan%
L1_SHADOW_HIT_POS12                                  0         -nan%                0         -nan%
L1_SHADOW_HIT_POS13                                  0         -nan%                0         -nan%
L1_SHADOW_HIT_POS14                                  0         -nan%                0         -nan%
L1_SHADOW_HIT_POS15                                  0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_SHADOW_STALLING_HIT_POS0                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS1                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS2                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS3                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS4                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS5                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS6                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS7                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS8                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS9                          0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS10                         0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS11                         0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS12                         0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS13                         0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS14                         0         -nan%                0         -nan%
L1_SHADOW_STALLING_HIT_POS15                         0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

L1_SHADOW_DEMAND_HIT_POS0                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS1                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS2                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS3                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS4                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS5                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS6                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS7                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS8                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS9                            0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS10                           0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS11                           0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS12                           0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS13                           0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS14                           0         -nan%                0         -nan%
L1_SHADOW_DEMAND_HIT_POS15                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_MLC_SENT                                   0                              0              

CORE_PREF_MLC_USED                                   0         -nan%                0         -nan%
CORE_PREF_MLC_PARTIAL_USED                           0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED                               0         -nan%                0         -nan%
CORE_PREF_MLC_DROPPED                                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_L1_SENT                                17536                          17536              

CORE_PREF_L1_USED                                17504       99.823%            17504       99.823%
CORE_PREF_L1_PARTIAL_USED                            0        0.000%                0        0.000%
CORE_PREF_L1_NOT_USED                               31        0.177%               31        0.177%
CORE_PREF_L1_DROPPED                                 0        0.000%                0        0.000%
                                                 17535      100.000%            17535      100.000%
                                                  0.00         0.08              0.00         0.08

TOTAL_MEM_LATENCY                          18434102256  1048762.7158      18434102256  1048762.7158

TOTAL_MEM_LATENCY_DEMAND                       1290624    30729.1429          1290624    30729.1429

TOTAL_MEM_LATENCY_PREF                     18432811632  1051201.1196      18432811632  1051201.1196

CORE_MEM_LATENCY                           18434102256  1048762.7158      18434102256  1048762.7158

CORE_MEM_LATENCY_DEMAND                        1290624    30729.1429          1290624    30729.1429

CORE_MEM_LATENCY_PREF                      18432811632  1051201.1196      18432811632  1051201.1196

CORE_MEM_LATENCY_IFETCH                        1225302        0.007%          1225302        0.007%
CORE_MEM_LATENCY_DFETCH                          65322        0.000%            65322        0.000%
CORE_MEM_LATENCY_DSTORE                              0        0.000%                0        0.000%
CORE_MEM_LATENCY_IPRF                                0        0.000%                0        0.000%
CORE_MEM_LATENCY_DPRF                      18432811632       99.993%      18432811632       99.993%
CORE_MEM_LATENCY_WB                                  0        0.000%                0        0.000%
CORE_MEM_LATENCY_WB_NODIRTY                          0        0.000%                0        0.000%
                                           18434102256      100.000%      18434102256      100.000%
                                                  4.00         0.01              4.00         0.01

CORE_MEM_STALLING_LATENCY_IFETCH                     0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_DFETCH                     0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_DSTORE                     0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_IPRF                       0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_DPRF                       0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_WB                         0         -nan%                0         -nan%
CORE_MEM_STALLING_LATENCY_WB_NODIRTY                 0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

TOTAL_L1_MISS_LATENCY                          1626316       92.5252          1626316       92.5252

TOTAL_L1_MISS_LATENCY_DEMAND                      2657       63.2619             2657       63.2619

TOTAL_L1_MISS_LATENCY_PREF                     1623659       92.5953          1623659       92.5953

CORE_L1_MISS_LATENCY                           1626316       92.5252          1626316       92.5252

CORE_L1_MISS_LATENCY_DEMAND                       2657       63.2619             2657       63.2619

CORE_L1_MISS_LATENCY_PREF                      1623659       92.5953          1623659       92.5953

CORE_EVICTED_L1_DEMAND                              40        3.353%               40        3.353%
CORE_EVICTED_L1_PREF_USED                         1153       96.647%             1153       96.647%
CORE_EVICTED_L1_PREF_NOT_USED                        0        0.000%                0        0.000%
                                                  1193      100.000%             1193      100.000%
                                                  0.97         0.03              0.97         0.03

CORE_EVICTED_MLC_DEMAND                              0         -nan%                0         -nan%
CORE_EVICTED_MLC_PREF_USED                           0         -nan%                0         -nan%
CORE_EVICTED_MLC_PREF_NOT_USED                       0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_MEM_LATENCY_AVE_DEMAND                       2461       61.5250             2461       61.5250

CORE_MEM_LATENCY_AVE_PREF_USED                  103850       90.0694           103850       90.0694

CORE_MEM_LATENCY_AVE_PREF_NOT_USED                   0          -nan                0          -nan

DRAM_LATENCY                                         0                              0              

TOTAL_DRAM_LATENCY                                   0                              0              

DRAM_CLOSED_PAGE_POLICY_CMD                          0                              0              

DRAM_ACTIVATE_STALLING                               0                              0              

DRAM_PRECHARGE_STALLING                              0                              0              

DRAM_PRECHARGE_STALLING_WAIT_CYCLES                  0                              0              

L1_STAY_DEMAND                                73884225  1847105.6250         73884225  1847105.6250

L1_STAY_PREF_USED                           2192738229  1901767.7615       2192738229  1901767.7615

L1_STAY_PREF_NOT_USED                                0          -nan                0          -nan

TOTAL_DATA_MISS_LATENCY                           1621                           1621              

TOTAL_DATA_MISS_COUNT                               30                             30              

CORE_PREF_L1_NOT_USED_LATENCY200                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY400                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY600                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY800                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY1000                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY1200                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY1400                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY1600                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_LATENCY1600MORE                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_L1_NOT_USED_DISTANCE_1                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_2                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_4                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_8                     0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_16                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_32                    0         -nan%                0         -nan%
CORE_PREF_L1_NOT_USED_DISTANCE_MORE                  0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_L1_USED_LATENCY200                      1096       95.056%             1096       95.056%
CORE_PREF_L1_USED_LATENCY400                         9        0.781%                9        0.781%
CORE_PREF_L1_USED_LATENCY600                        11        0.954%               11        0.954%
CORE_PREF_L1_USED_LATENCY800                        10        0.867%               10        0.867%
CORE_PREF_L1_USED_LATENCY1000                       12        1.041%               12        1.041%
CORE_PREF_L1_USED_LATENCY1200                       12        1.041%               12        1.041%
CORE_PREF_L1_USED_LATENCY1400                        3        0.260%                3        0.260%
CORE_PREF_L1_USED_LATENCY1600                        0        0.000%                0        0.000%
CORE_PREF_L1_USED_LATENCY1600MORE                    0        0.000%                0        0.000%
                                                  1153      100.000%             1153      100.000%
                                                  0.16         0.77              0.16         0.77

CORE_PREF_L1_USED_DISTANCE_1                         0        0.000%                0        0.000%
CORE_PREF_L1_USED_DISTANCE_2                         0        0.000%                0        0.000%
CORE_PREF_L1_USED_DISTANCE_4                         4        0.347%                4        0.347%
CORE_PREF_L1_USED_DISTANCE_8                        16        1.388%               16        1.388%
CORE_PREF_L1_USED_DISTANCE_16                     1133       98.265%             1133       98.265%
CORE_PREF_L1_USED_DISTANCE_32                        0        0.000%                0        0.000%
CORE_PREF_L1_USED_DISTANCE_MORE                      0        0.000%                0        0.000%
                                                  1153      100.000%             1153      100.000%
                                                  3.98         0.17              3.98         0.17

CORE_PREF_L1_DEMAND_LATENCY300                      40      100.000%               40      100.000%
CORE_PREF_L1_DEMAND_LATENCY400                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY500                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY600                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY700                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY800                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY900                       0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY1000                      0        0.000%                0        0.000%
CORE_PREF_L1_DEMAND_LATENCY1000MORE                  0        0.000%                0        0.000%
                                                    40      100.000%               40      100.000%
                                                  0.00         0.00              0.00         0.00

CORE_PREF_MLC_NOT_USED_LATENCY200                    0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY400                    0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY600                    0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY800                    0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1000                   0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1200                   0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1400                   0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1600                   0         -nan%                0         -nan%
CORE_PREF_MLC_NOT_USED_LATENCY1600MORE               0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_MLC_USED_LATENCY200                        0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY400                        0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY600                        0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY800                        0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY1000                       0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY1200                       0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY1400                       0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY1600                       0         -nan%                0         -nan%
CORE_PREF_MLC_USED_LATENCY1600MORE                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_PREF_MLC_DEMAND_LATENCY300                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY400                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY500                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY600                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY700                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY800                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY900                      0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY1000                     0         -nan%                0         -nan%
CORE_PREF_MLC_DEMAND_LATENCY1000MORE                 0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

TOTAL_BATCH_FORMED                                   0                              0              

TOTAL_BATCH_MEM_REQ_MARKED                           0          -nan                0          -nan

CORE_BATCH_MEM_REQ_MARKED                            0          -nan                0          -nan

CORE_BATCH_MEM_REQ_MARKED_DEMAND                     0          -nan                0          -nan

CORE_BATCH_MEM_REQ_MARKED_PREF                       0          -nan                0          -nan

DRAM_ROW_BATCHES                                     0                              0              

REJECTED_QUEUE_MLC                                   0                              0              

REJECTED_QUEUE_L1                                    0                              0              

REJECTED_QUEUE_BUS_OUT                               0                              0              

LEADING_LOAD_LATENCY                                 0        0.0000                0        0.0000

LEADING_LOADS                                        0        0.0000                0        0.0000

MEM_REQ_CRITICAL_PATH_LENGTH                         0        0.0000                0        0.0000

TOTAL_MEM_REQ_LATENCY                                0                              0              

TOTAL_CRITICAL_MEM_REQ_LATENCY                       0          -nan                0          -nan

TOTAL_CRITICAL_BANK_LATENCY                          0          -nan                0          -nan

TOTAL_MEMORY_SLACK                                   0        0.0000                0        0.0000

TOTAL_CHIP_UTILIZATION                               0        0.0000                0        0.0000

CHIP_BUSY_UNDER_CRITICAL_REQS                        0        0.0000                0        0.0000

PERF_PRED_NUM_STAT_RESETS                            0                              0              

PERF_PRED_RESET_STATS_CYCLE                          0                              0              

PERF_PRED_CYCLE                                2100778                        2100778              

ESTIMATED_ALONE_CYCLES                               0        0.0000                0        0.0000

NUM_WINDOWS_WITH_DCACHE_MISS                     16007                          16007              

LONGEST_DCACHE_MISS_CHAIN                        17328                          17328              

NUM_DCACHE_MISSES_IN_WINDOW_1                    14495       90.554%            14495       90.554%
NUM_DCACHE_MISSES_IN_WINDOW_2                     1502        9.383%             1502        9.383%
NUM_DCACHE_MISSES_IN_WINDOW_3                        7        0.044%                7        0.044%
NUM_DCACHE_MISSES_IN_WINDOW_4                        1        0.006%                1        0.006%
NUM_DCACHE_MISSES_IN_WINDOW_5                        1        0.006%                1        0.006%
NUM_DCACHE_MISSES_IN_WINDOW_6                        0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_7                        0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_8                        0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_9                        0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_10                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_11                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_12                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_13                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_14                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_15                       0        0.000%                0        0.000%
NUM_DCACHE_MISSES_IN_WINDOW_16_OR_MORE               1        0.006%                1        0.006%
                                                 16007      100.000%            16007      100.000%
                                                  0.10         0.31              0.10         0.31

DCACHE_MLP_IN_WINDOW_1_0                         15802       98.719%            15802       98.719%
DCACHE_MLP_IN_WINDOW_1_5                             4        0.025%                4        0.025%
DCACHE_MLP_IN_WINDOW_2_0                           197        1.231%              197        1.231%
DCACHE_MLP_IN_WINDOW_2_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_3_0                             3        0.019%                3        0.019%
DCACHE_MLP_IN_WINDOW_3_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_4_0                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_4_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_5_0                             1        0.006%                1        0.006%
DCACHE_MLP_IN_WINDOW_5_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_6_0                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_6_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_7_0                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_7_5                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_8_0                             0        0.000%                0        0.000%
DCACHE_MLP_IN_WINDOW_8_5_OR_MORE                     0        0.000%                0        0.000%
                                                 16007      100.000%            16007      100.000%
                                                  0.03         0.23              0.03         0.23

PARAM_CHIP_CYCLE_TIME                                0                              0              

PARAM_CORE_CYCLE_TIME                           312500                         312500              

PARAM_L1_CYCLE_TIME                             312500                         312500              

PARAM_MEMORY_CYCLE_TIME                         833333                         833333              

MEM_REQ_NON_SCHEDULED__0                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED__4                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED__8                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_12                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_16                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_20                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_24                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_28                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_32                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_36                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_40                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_44                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_48                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_52                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_56                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_60                             0         -nan%                0         -nan%
MEM_REQ_NON_SCHEDULED_64                             0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_REQ_DEMANDS__0                             2100698       99.996%          2100698       99.996%
MEM_REQ_DEMANDS__4                                  80        0.004%               80        0.004%
MEM_REQ_DEMANDS__8                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_12                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_16                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_20                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_24                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_28                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_32                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_36                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_40                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_44                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_48                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_52                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_56                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_60                                   0        0.000%                0        0.000%
MEM_REQ_DEMANDS_64                                   0        0.000%                0        0.000%
                                               2100778      100.000%          2100778      100.000%
                                                  0.00         0.01              0.00         0.01

MEM_REQ_PREFS__0                               2012630       95.804%          2012630       95.804%
MEM_REQ_PREFS__4                                 53199        2.532%            53199        2.532%
MEM_REQ_PREFS__8                                 33949        1.616%            33949        1.616%
MEM_REQ_PREFS_12                                  1000        0.048%             1000        0.048%
MEM_REQ_PREFS_16                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_20                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_24                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_28                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_32                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_36                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_40                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_44                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_48                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_52                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_56                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_60                                     0        0.000%                0        0.000%
MEM_REQ_PREFS_64                                     0        0.000%                0        0.000%
                                               2100778      100.000%          2100778      100.000%
                                                  0.06         0.30              0.06         0.30

MEM_REQ_WRITEBACKS__0                          2100778      100.000%          2100778      100.000%
MEM_REQ_WRITEBACKS__4                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS__8                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_12                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_16                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_20                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_24                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_28                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_32                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_36                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_40                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_44                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_48                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_52                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_56                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_60                                0        0.000%                0        0.000%
MEM_REQ_WRITEBACKS_64                                0        0.000%                0        0.000%
                                               2100778      100.000%          2100778      100.000%
                                                  0.00         0.00              0.00         0.00

MEM_REQ_DEMAND_CYCLES                           336265                         336265              

MEM_REQ_PREF_CYCLES                            1992153                        1992153              

MEM_REQ_WB_CYCLES                               262447                         262447              

DRAM_CHANNEL_REQS                                    0                              0              

DRAM_CHANNEL_CRIT_REQS                               0                              0              

DRAM_CHANNEL_CRIT_DIR_SWITCHES                       0                              0              

DRAM_BANK_CRIT_REQS                                  0                              0              

DRAM_INSTA_MLP_SAMPLES                               0                              0              

DRAM_INSTA_MLP_UNIQUE_REQS                           0          -nan                0          -nan

DRAM_INST_MLP_HITS_NORM_SPREAD_TIMES_1000             0          -nan                0          -nan

DRAM_GLOBAL_MLP                                      0          -nan                0          -nan

DRAM_GLOBAL_MLP_0                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_1                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_2                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_3                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_4                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_5                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_6                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_7                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_8                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_9                                    0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_10                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_11                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_12                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_13                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_14                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_15                                   0         -nan%                0         -nan%
DRAM_GLOBAL_MLP_16                                   0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_TOTAL_GLOBAL_MLP_0                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_1                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_2                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_3                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_4                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_5                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_6                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_7                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_8                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_9                              0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_10                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_11                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_12                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_13                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_14                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_15                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_16                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_17                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_18                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_19                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_20                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_21                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_22                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_23                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_24                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_25                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_26                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_27                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_28                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_29                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_30                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_31                             0         -nan%                0         -nan%
DRAM_TOTAL_GLOBAL_MLP_32                             0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

UNIQUE_ROWS_PER_BANK_0                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_1                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_2                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_3                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_4                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_5                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_6                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_7                               0         -nan%                0         -nan%
UNIQUE_ROWS_PER_BANK_MORE                            0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORE_UNIQUE_ROWS_PER_BANK_0                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_1                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_2                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_3                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_4                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_5                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_6                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_7                          0         -nan%                0         -nan%
CORE_UNIQUE_ROWS_PER_BANK_MORE                       0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

CORES_PER_BANK_0                                     0         -nan%                0         -nan%
CORES_PER_BANK_1                                     0         -nan%                0         -nan%
CORES_PER_BANK_2                                     0         -nan%                0         -nan%
CORES_PER_BANK_3                                     0         -nan%                0         -nan%
CORES_PER_BANK_4                                     0         -nan%                0         -nan%
CORES_PER_BANK_5                                     0         -nan%                0         -nan%
CORES_PER_BANK_6                                     0         -nan%                0         -nan%
CORES_PER_BANK_7                                     0         -nan%                0         -nan%
CORES_PER_BANK_MORE                                  0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_BANKS_WITH_REQS_0                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_1                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_2                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_3                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_4                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_5                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_6                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_7                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_8                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_9                                0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_10                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_11                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_12                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_13                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_14                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_15                               0         -nan%                0         -nan%
MEM_BANKS_WITH_REQS_16                               0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_BANKS_WITH_REQS                                  0                              0              

DRAM_CHANNEL_IN_DEMAND                               0                              0              

DRAM_BUS_IN_DEMAND                                   0                              0              

DRAM_BANK_IN_DEMAND                                  0                              0              

DRAM_BANK_IN_DEMAND_STALLING                         0                              0              

DRAM_ANY_BANK_IN_DEMAND                              0                              0              

DRAM_BANK_IN_DEMAND_BANK_0                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_1                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_2                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_3                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_4                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_5                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_6                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_7                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_8                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_9                           0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_10                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_11                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_12                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_13                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_14                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_15                          0         -nan%                0         -nan%
DRAM_BANK_IN_DEMAND_BANK_16                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_CONTENTION_BUS                                  0          -nan                0          -nan

DRAM_CONTENTION_BANKS                                0          -nan                0          -nan

DRAM_CONTENTION_FAW                                  0          -nan                0          -nan

DRAM_CONTENTION_BANKS_TIMES_1000                     0          -nan                0          -nan

DRAM_STALL_OTHER_CORE                                0                              0              

DRAM_STALLED_BY_OTHER_CORE                           0                              0              

DRAM_MP_CRIT_PATH                                    0                              0              

DRAM_MP_CRIT_PATH_BUS                                0          -nan                0          -nan

DRAM_MP_CRIT_PATH_BANK                               0          -nan                0          -nan

DRAM_MP_CRIT_PATH_BANK_TRAS                          0          -nan                0          -nan

DRAM_MP_CRIT_PATH_FAW                                0          -nan                0          -nan

DRAM_BLACK_BOX_SERVICE_TIMES_1000                    0                              0              

DRAM_BLACK_BOX_REQS_BUSY_0                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_1                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_2                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_3                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_4                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_5                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_6                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_7                           0         -nan%                0         -nan%
DRAM_BLACK_BOX_REQS_BUSY_8                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

NUM_MEM_SCHED_DECISIONS                              0                              0              

MEM_REQ_NON_SCHEDULED_CANDIDATES                     0          -nan                0          -nan

NUM_MEM_SCHED_DECISIONS_PER_BANK                     0                              0              

MEM_REQ_NON_SCHEDULED_CANDIDATES_PER_BANK             0          -nan                0          -nan

ROW_BUFFER_HITS_BANK_0                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_1                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_2                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_3                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_4                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_5                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_6                               0         -nan%                0         -nan%
ROW_BUFFER_HITS_BANK_7                               0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

ROW_BUFFER_CONFLICTS_BANK_0                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_1                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_2                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_3                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_4                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_5                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_6                          0         -nan%                0         -nan%
ROW_BUFFER_CONFLICTS_BANK_7                          0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

MEM_BANK_WAITING_CYCLES                              0                              0              

MEM_WAITING_CYCLES_TIMES_840                         0                              0              

MEM_PROB_WAITING_CYCLES                              0                              0              

DRAM_SCHED_QUANTA                                    0                              0              

DRAM_SCHED_CORE_PRIORITY_0                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_1                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_2                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_3                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_4                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_5                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_6                           0         -nan%                0         -nan%
DRAM_SCHED_CORE_PRIORITY_7                           0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_SCHED_CMD_SCHEDULED                             0          -nan                0          -nan

DRAM_SCHED_DIFF_CORE_AVAILABLE                       0          -nan                0          -nan

DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_1                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_2                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_3                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_4                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_5                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_6                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_7                0         -nan%                0         -nan%
DRAM_SCHED_DIFF_CORE_DECIDING_INPUT_8                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_BANK_WAIT_CYCLES_ROW_CONFLICT                   0                              0              

DRAM_BANK_WAIT_CYCLES_ROW_MISS                       0                              0              

DRAM_BANK_WAIT_CYCLES_ROW_HIT                        0                              0              

DRAM_ROW_OPEN_WAIT                                   0                              0              

MEM_QUEUE_ARRIVAL_DISTANCE_0                         0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_10                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_20                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_30                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_40                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_50                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_60                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_70                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_80                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_90                        0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_100                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_110                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_120                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_130                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_140                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_150                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_160                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_170                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_180                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_190                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_200                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_210                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_220                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_230                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_240                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_250                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_260                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_270                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_280                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_290                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_300                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_310                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_320                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_330                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_340                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_350                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_360                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_370                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_380                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_390                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_400                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_410                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_420                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_430                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_440                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_450                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_460                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_470                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_480                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_490                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_500                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_510                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_520                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_530                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_540                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_550                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_560                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_570                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_580                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_590                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_600                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_610                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_620                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_630                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_640                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_650                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_660                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_670                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_680                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_690                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_700                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_710                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_720                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_730                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_740                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_750                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_760                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_770                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_780                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_790                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_800                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_810                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_820                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_830                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_840                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_850                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_860                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_870                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_880                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_890                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_900                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_910                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_920                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_930                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_940                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_950                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_960                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_970                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_980                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_990                       0         -nan%                0         -nan%
MEM_QUEUE_ARRIVAL_DISTANCE_1000                      0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

EQUAL_USE_QUANTUMS                                   0                              0              

EQUAL_USE_BW_MEASURE_PERIODS                         0                              0              

EQUAL_USE_BW                                         0                              0              

EQUAL_USE_BOTTLENECK_BUS                             0         -nan%                0         -nan%
EQUAL_USE_BOTTLENECK_BANK                            0         -nan%                0         -nan%
EQUAL_USE_BOTTLENECK_FAW                             0         -nan%                0         -nan%
EQUAL_USE_BOTTLENECK_BUS_PLUS_FAW                    0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

EQUAL_USE_BW_BUS                                     0                              0              

EQUAL_USE_BW_BANK                                    0                              0              

EQUAL_USE_BW_FAW                                     0                              0              

EQUAL_USE_BW_BUS_PLUS_FAW                            0                              0              

EQUAL_USE_BW_BUS_PLUS_FAW2                           0                              0              

EQUAL_USE_BW_BUS_PLUS_FAW3                           0                              0              

EQUAL_USE_BW_CRIT_PATH                               0                              0              

EQUAL_USE_BW_BLACK_BOX                               0                              0              

DRAM_BANK_SERVICE                                    0                              0              

DRAM_CONTENDED_BANK_SERVICE                          0                              0              

DRAM_BUS_DIR_SWITCHES                                0                              0              

DRAM_ACTIVATE_TO_COLUMN_LATENCY                      0                              0              

DRAM_ACTIVATE_TO_READ                                0                              0              

DRAM_ACTIVATE_TO_READ_LATENCY                        0          -nan                0          -nan

DRAM_ACTIVATE_TO_WRITE                               0                              0              

DRAM_ACTIVATE_TO_WRITE_LATENCY                       0          -nan                0          -nan

EQUAL_USE_PRIORITY_0                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_1                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_2                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_3                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_4                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_5                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_6                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_7                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_8                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_9                                 0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_10                                0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_11                                0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_12                                0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_13                                0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_14                                0         -nan%                0         -nan%
EQUAL_USE_PRIORITY_15                                0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_ROW_ACCESSES_0                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_1                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_2                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_3                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_4                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_5                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_6                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_7                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_8                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_9                                  0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_10                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_11                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_12                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_13                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_14                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_15                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_16                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_17                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_18                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_19                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_20                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_21                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_22                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_23                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_24                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_25                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_26                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_27                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_28                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_29                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_30                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_31                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_32                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_33                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_34                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_35                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_36                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_37                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_38                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_39                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_40                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_41                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_42                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_43                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_44                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_45                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_46                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_47                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_48                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_49                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_50                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_51                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_52                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_53                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_54                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_55                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_56                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_57                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_58                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_59                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_60                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_61                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_62                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_63                                 0         -nan%                0         -nan%
DRAM_ROW_ACCESSES_64                                 0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_NUM_REQS_0_TOTAL                                0                              0              

DRAM_NUM_REQS_1_TOTAL                                0                              0              

DRAM_NUM_REQS_2_TOTAL                                0                              0              

DRAM_NUM_REQS_3_TOTAL                                0                              0              

DRAM_NUM_REQS_4_TOTAL                                0                              0              

DRAM_NUM_REQS_5_TOTAL                                0                              0              

DRAM_NUM_REQS_6_TOTAL                                0                              0              

DRAM_NUM_REQS_7_TOTAL                                0                              0              

DRAM_NUM_REQS_8_TOTAL                                0                              0              

DRAM_NUM_REQS_9_TOTAL                                0                              0              

DRAM_NUM_REQS_10_TOTAL                               0                              0              

DRAM_NUM_REQS_11_TOTAL                               0                              0              

DRAM_NUM_REQS_12_TOTAL                               0                              0              

DRAM_NUM_REQS_13_TOTAL                               0                              0              

DRAM_NUM_REQS_14_TOTAL                               0                              0              

DRAM_NUM_REQS_15_TOTAL                               0                              0              

DRAM_NUM_REQS_16_TOTAL                               0                              0              

DRAM_NUM_REQS_17_TOTAL                               0                              0              

DRAM_NUM_REQS_18_TOTAL                               0                              0              

DRAM_NUM_REQS_19_TOTAL                               0                              0              

DRAM_NUM_REQS_20_TOTAL                               0                              0              

DRAM_NUM_REQS_21_TOTAL                               0                              0              

DRAM_NUM_REQS_22_TOTAL                               0                              0              

DRAM_NUM_REQS_23_TOTAL                               0                              0              

DRAM_NUM_REQS_24_TOTAL                               0                              0              

DRAM_NUM_REQS_25_TOTAL                               0                              0              

DRAM_NUM_REQS_26_TOTAL                               0                              0              

DRAM_NUM_REQS_27_TOTAL                               0                              0              

DRAM_NUM_REQS_28_TOTAL                               0                              0              

DRAM_NUM_REQS_29_TOTAL                               0                              0              

DRAM_NUM_REQS_30_TOTAL                               0                              0              

DRAM_NUM_REQS_31_TOTAL                               0                              0              

DRAM_NUM_REQS_32_TOTAL                               0                              0              

DRAM_NUM_REQS_0_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_0_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_0_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_0_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_0_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_0_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_0_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_1_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_1_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_1_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_1_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_1_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_1_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_1_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_2_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_2_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_2_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_2_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_2_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_2_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_2_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_3_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_3_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_3_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_3_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_3_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_3_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_3_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_4_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_4_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_4_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_4_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_4_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_4_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_4_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_5_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_5_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_5_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_5_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_5_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_5_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_5_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_6_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_6_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_6_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_6_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_6_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_6_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_6_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_7_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_7_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_7_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_7_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_7_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_7_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_7_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_8_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_8_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_8_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_8_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_8_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_8_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_8_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_9_IFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_9_DFETCH                               0          -nan                0          -nan

DRAM_NUM_REQS_9_DSTORE                               0          -nan                0          -nan

DRAM_NUM_REQS_9_IPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_9_DPRF                                 0          -nan                0          -nan

DRAM_NUM_REQS_9_WB                                   0          -nan                0          -nan

DRAM_NUM_REQS_9_WB_NODIRTY                           0          -nan                0          -nan

DRAM_NUM_REQS_10_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_10_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_10_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_10_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_10_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_10_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_10_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_11_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_11_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_11_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_11_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_11_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_11_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_11_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_12_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_12_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_12_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_12_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_12_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_12_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_12_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_13_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_13_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_13_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_13_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_13_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_13_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_13_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_14_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_14_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_14_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_14_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_14_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_14_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_14_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_15_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_15_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_15_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_15_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_15_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_15_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_15_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_16_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_16_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_16_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_16_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_16_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_16_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_16_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_17_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_17_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_17_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_17_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_17_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_17_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_17_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_18_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_18_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_18_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_18_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_18_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_18_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_18_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_19_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_19_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_19_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_19_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_19_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_19_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_19_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_20_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_20_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_20_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_20_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_20_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_20_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_20_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_21_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_21_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_21_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_21_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_21_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_21_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_21_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_22_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_22_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_22_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_22_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_22_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_22_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_22_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_23_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_23_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_23_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_23_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_23_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_23_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_23_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_24_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_24_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_24_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_24_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_24_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_24_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_24_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_25_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_25_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_25_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_25_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_25_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_25_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_25_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_26_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_26_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_26_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_26_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_26_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_26_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_26_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_27_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_27_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_27_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_27_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_27_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_27_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_27_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_28_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_28_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_28_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_28_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_28_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_28_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_28_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_29_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_29_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_29_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_29_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_29_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_29_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_29_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_30_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_30_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_30_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_30_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_30_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_30_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_30_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_31_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_31_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_31_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_31_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_31_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_31_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_31_WB_NODIRTY                          0          -nan                0          -nan

DRAM_NUM_REQS_32_IFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_32_DFETCH                              0          -nan                0          -nan

DRAM_NUM_REQS_32_DSTORE                              0          -nan                0          -nan

DRAM_NUM_REQS_32_IPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_32_DPRF                                0          -nan                0          -nan

DRAM_NUM_REQS_32_WB                                  0          -nan                0          -nan

DRAM_NUM_REQS_32_WB_NODIRTY                          0          -nan                0          -nan

DRAM_BOTTLENECK_BUS_0                                0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_10                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_20                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_30                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_40                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_50                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_60                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_70                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_80                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_90                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_BUS_100                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_BOTTLENECK_BANKS_0                              0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_10                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_20                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_30                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_40                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_50                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_60                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_70                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_80                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_90                             0         -nan%                0         -nan%
DRAM_BOTTLENECK_BANKS_100                            0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_BOTTLENECK_FAW_0                                0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_10                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_20                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_30                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_40                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_50                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_60                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_70                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_80                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_90                               0         -nan%                0         -nan%
DRAM_BOTTLENECK_FAW_100                              0         -nan%                0         -nan%
                                                     0         -nan%                0         -nan%
                                                  -nan         -nan              -nan         -nan

DRAM_ROW_HIT_GEN_AFTER_ROW_OPEN_STALLING             0                              0              



